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APLUS
MAKE YOUR PRODUCTION A-PLUS
APExx12 Series DATA SHEET
APLUS
INTEGRATED CIRCUITS INC.
Sales E-mail: sales@aplusinc.com.tw Technology E-mail: service@aplusinc.com.tw
Address: 3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei, Taiwan 115, R.O.C. (115) 32 3 10. TEL: 886-2-2782-9266 FAX: 886-2-2782-9255 WEBSITE : http: //www.aplusinc.com.tw
APExx12 Series
1.0 General Description
The APExx12 series are very low cost voice and melody synthesizer with 4-bits CPU. They have various features including 4-bits ALU, ROM, RAM, I/O ports, timers, clock generator, voice and melody synthesizer, and PWM (Direct drive) or D/A current outputs, etc. The audio synthesizer contains one voice-channel and two melody-channels. Furthermore, they consist of 27 instructions in these devices. With CMOS technology and halt function can minimize power dissipation. Their architectures are similar to RISC, with two stages of instruction pipeline. They allow all instructions to be executed in a single cycle, except for program branches and data table read instructions (which need two instruction cycles).
2.0 Features
(1) Single power supply can operate from 2.4V to 5.5V at 4MHz or 8MHz. (2) Program ROM: 16k x 10 bits (3) 1 set of 16-bits DPR can access up to 64k x 10 bits melody data memory space, and 1 set of 18-bits VPR can access up to 256k x 10 bits voice data memory space. Product APE0612 APE1012 APE1512 APE2012 APE3112 APE4112 APE5212 APE6312 APE7312 APE8412 (4) Data Registers: a). 128 x 4-bit data RAM (00-7Fh) b). Unbanked special function registers (SFR) range: 00h-2Fh (5) I/O Ports: a). PRA: 4-bits I/O Port A (10h) can be programmed to input/output individually. (Register control) b). PRB: 4-bits I/O Port B (13h) can be configured to input/output individually. (Mask option) c). PRD: 4-bits I/O Port D (15h) can be programmed to input/output individually. (Register control) (6) On-chip clock generator: Resistive Clock Drive (RM) (7) Timer: 1-set Voice Interrupt (Timer0: a 9-bits auto-reload timer/counter). (8) Stack: 2-level subroutine nesting. (9) Built-in 4 Level Volume Control can be programmed. 1 Rev 1.3 2003/8/18 Voice Duration (sec) Voice Pointer (VPR) ROM Size (10-bit) 6 10 15 20 31 41 52 63 73 84 14-bits 15-bits 16-bits 16-bits 17-bits 17-bits 18-bits 18-bits 18-bits 18-bits 20k 32k 48k 64k 96k 128k 160k 192k 224k 256k
APExx12 Series
(10) Built-in 8 Level DAC current output can be configured. (Mask option) (11) Built-in IR Carry Output: Port B[1] can be configured as IR pin by 38k / 56kHz. (Mask option) (12) External Reset: Port B[3] can be configured as reset pin. (Mask opton) (13) HALT and Release from HALT function to reduce power consumption (14) Watch Dog Timer (WDT) (15) Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles (16) Number of instruction: 27 (17) DAC: 1 channel voice and dual tone melody synthesizer (One 9-bits Cout or 8-bits PWM output).
FIGURE 1 : ROM Map of APExx12 Series PC[13:0]
14-bit x 2 STACK 16-bit Data Pointer 18-bit Voice Pointer Reset Vector
00000h 000FEh 000FFh-00400h 00401h
Reserved for Testing
00000h-03FFFh 00000h-0FFFFh Data ROM for Melody Program ROM
00000h-5FFFFh Voice ROM for Voice
2
Rev 1.3
2003/8/18
APExx12 Series
3.0 Pin Description
Pad Name PWM2/Cout PWM1 Vdd1~2 PRA0~3 PRD0~3 PRB0, PRB2 Pin Attr. O O Power I/O Description PWM2 output, or Current Output of Audio. PWM1 output. Power supply during operation. I/O port can be programmed to input/output individually. Input type with weak pull-low or fix-input-floating capability. Buffer Output type. I/O port can be configured to input/output individually. Input type with weak pull-low or fix-input-floating capability. Buffer Output type. I/O port can be configured to input/output individually. Input type with weak pull-low or fix-input-floating capability. Buffer Output type. Mask option selected as an IR Carrier Output with 38k / 56kHz I/O port can be configured to input/output individually. Input type with weak pull-low or fix-input-floating capability. Buffer Output type. Mask option selected as an external RESET pin with weak pull-low capability. RM mode Oscillator input Ground Potential
I/O
PRB1 / IR
I/O
PRB3 / Reset
I/O
OSC GND1~3
I Power
4.0 DC Characteristics
Symbol Vdd Isb Iop Iih Ioh Iol Cout dF/F dF/F Parameter Operating voltage Supply current Standby Operating Vdd 3 4.5 3 4.5 3 4.5 3 4.5 3 4.5 3 4.5 -5 -10 Min. 2.4 Typ. 3 Max. 5.5 1 1 Unit V uA mA uA Condition depending on Freq. 4MHz, RM, in HALT Mode 4MHz, RM, IO Floating Input ports with weak pull-low 4MHz, RM (IO ports) 4MHz, RM (Full scale) Fosc(3v- 2.4v) Fosc (3v) Vdd=3V, Rosc=180k, 4MHz
Input current (Internal pull low) Output-high current Output-low current DAC output current (8-level option) Frequency stability Fosc lot variation
2 7 3 10 -3 -10 7 19 0.8 ~ 4.8 0.9 ~ 6.5 5 10
mA
mA % %
3
Rev 1.3
2003/8/18
APExx12 Series
FIGURE 2 : Frequency vs. Rosc (at 3V) Resistor (Rosc ohms) Frequency (MHz) 110k 14.84 200k 8.25 300k 5.54 430k 3.92
R o sc vs F re q.
20
Freq. (MHz)
15 10 5 0
0 100
1 4 .8 4 8 .25 5 .54 3 .92
200
300
400
500
R os c (k o h m )
5.0 Application Circuit
4
Rev 1.3
2003/8/18
APExx12 Series
6.0 Bonding Diagram
ROM
1
Y
PWM1
PRD3 PRD2
20 19 18
2
Vdd2
Pad Size : 80 um x 80 um * The IC substrate must be connected to GND.
PRD1 PRD0
17
3
PWM2/Cout OSC 16 15
4 GND2 5 (0,0)
GND3 PRA0 6 PRA1 7 PRA2 8 PRA3 9 PRB0 10 PRB1 11 PRB2 12
GND1
PRB3 13
Vdd1 14
X
Pad # 1 2 3 4 5 6 7 8 9 10 Chip Size :
Pad Name PWM1 Vdd2 PWM2/ Cout GND3 GND2 PRA0 PRA1 PRA2 PRA3 PRB0
X 57 58 58 58 65 175 285 395 505 615
Y 865 670 386 235 87 87 87 87 87 87
Pad # 11 12 13 14 15 16 17 18 19 20
Pad Name PRB1 PRB2 PRB3 Vdd1 GND1 OSC PRD0 PRD1 PRD2 PRD3
X 725 835 945 1055 1059 1059 1059 1059 1059 1059
Y 87 87 87 87 241 351 461 571 681 791
APE0612 : 1230 um x 1530 um, APE1512 : 1230 um x 1758 um, APE3112 : 1230 um x 2210 um, APE5212 : 1230 um x 3116 um, APE7312 : 1230 um x 3116 um,
APE1012 : 1230 um x 1530 um APE2012 : 1230 um x 1758 um APE4112 : 1230 um x 2210 um APE6312 : 1230 um x 3116 um APE8412 : 1230 um x 3116 um 5 Rev 1.3 2003/8/18

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